Non-volatile memory control

ABSTRACT

Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/800,974, filed May 8, 2007 and issued as U.S. Pat. No. 7,944,762 onMay 17, 2011, which is a continuation of U.S. application Ser. No.10/867,800 filed Jun. 14, 2004 now U.S. Pat. No. 7,215,580, issued onMay 8, 2007, which is a continuation of U.S. application Ser. No.10/260,074 filed Sep. 27, 2002 now U.S. Pat. No. 6,751,155 issued Jun.15, 2004, which claimed the benefit of the priority date of BritishApplication No. 0123416.0, entitled “Non-Volatile Memory Control”, filedon Sep. 28, 2001, the contents of which are incorporated by referenceherein in their entirety.

TECHNICAL FIELD

The present invention relates generally to a solid state memory systemfor data storage and retrieval, and to a memory controller forcontrolling access to a non-volatile memory of a solid state memorysystem and particularly to a method and apparatus of fast access of thedata in the memory system with precise control of power consumptionincluding the control of flash (or non-volatile) memory accesses.

BACKGROUND

It is well known to use solid state memory systems to try to emulatemagnetic disc storage devices in computer systems. It is an aim of theindustry to try to increase the speed of operation of solid state memorysystems to better emulate magnetic disc storage.

A typical memory system comprises a non-volatile (Flash) memory and acontroller. The memory has individually addressable sectors where amemory sector is a group of flash memory locations which is allocatedfor storage of one Logical Sector. A memory sector need not be aphysical partition within Flash memory, not contiguous Flash memorylocations, so that the memory sector address may be a virtual addressconveniently used by the controller. The controller writes datastructures to and reads data structures from the memory, and translateslogical addresses received from the host to physical (virtual) addressesof the memory sectors in the memory.

An example of such a memory system is illustrated by the Memory Systemof patent publication number WO 00/49488. In FIG. 1 (prior art), thereis illustrated the timing of various operations involved in a multiplesector write to interleaved flash chips forming a flash array describedfor the memory system of WO 00/49488.

However in many systems, and in particular systems such as portablecomputers, the maximum level of electrical current is a very importantparameter defining the system design, efficiency and cost. For systems,which include memory storage devices, the number of flash memory chipsactive at the time is a major factor defining the current level. It istherefore important to control the maximum value of electrical currentlevel to avoid high peaks, which can cause higher requirements to thehost system power supply. It is also important to be able to change themaximum current level and to compromise on performance if required.

Thus, a need arises to obviate or mitigate at least one of theaforementioned problems.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic representation of timing operations of a priorart memory system;

FIG. 2 illustrates a memory system and associated host system inaccordance with an embodiment of the present invention;

FIG. 3 shows a schematic representation of the hardware architecture ofthe controller of the memory system of FIG. 2;

FIG. 4 shows a schematic representation of the firmware executed in themicroprocessor of the controller of FIG. 3;

FIG. 5A shows a schematic representation of the data write operationused by the controller of FIG. 3;

FIG. 5B illustrates read and write pointer operations;

FIG. 6 shows a schematic representation of the hierarchy of mappingstructures of the address translation process used by the controller ofFIG. 3;

FIG. 7 illustrates a schematic representation of a method of schedulingthe transfer of sector data according to a first embodiment of thepresent invention;

FIG. 8 depicts a schematic representation of a method of scheduling thetransfer of sector data according to second embodiment of the presentinvention;

FIG. 9 shows a schematic representation of a method of scheduling thetransfer of sector data according to third embodiment of the presentinvention;

FIG. 10 shows a schematic representation of a method of scheduling thetransfer of sector data according to fourth embodiment of the presentinvention;

FIG. 11 shows a schematic representation of a method of scheduling thetransfer of data whilst limiting the number of active arrays accordingto the present invention;

FIG. 12 shows an alternative memory system arrangement in accordancewith another embodiment of the present invention.

DETAILED DESCRIPTION

A Flash disk device, such as that shown in FIG. 2, is a memory systemwhich presents the logical characteristics of a disk storage device to ahost system 12, and which uses Flash semiconductor memory 20 as itsphysical data storage medium. A Flash disk memory system 10 requires acontroller 12 to manage the physical storage medium of the system 10according to algorithms which create the logical characteristics of adisk and, in this case, it is the flash memory 20 and controller 16which are connected by physical interface 16 which form the memorysystem 10. The controller 16 of the memory system 10 connects the system10 to the host 12 via logical interface 14.

In this case the flash memory 20 comprises a plurality of flash chipswhich are formed of a plurality of flash blocks. The logical interface14 to the memory system 10 allows data to be written to and read fromthe system 10 in fixed-size units called sectors, each containing 512bytes of data, which can be randomly accessed. Each sector is identifiedby a logical address which in this case is a sequential Logical BlockAddress (LBA).

In the present arrangement data may be written to a sector even if thesector already includes data. The protocols at the logical interface 14can, in this case, support, read or write access to the system 10 inmulti-sector blocks of logically contiguous sector addresses, theseprotocols conform to industry standards such as ATA, CompactFlash, orMultiMediaCard thus allowing the memory system 10 to be interchangeablebetween different host systems and not limited to use with host 12.

The physical interface 18 from controller 16 to Flash Memory 20 allowsdata to be written to and read from Flash memory 20 in fixed-size unitswhich in this case are called physical sectors and each of which can beaccessed randomly with each typically having sufficient capacity for 512bytes of data from the host system plus 16 bytes of overhead dataappended by the controller 16. Each physical sector is identified by aphysical sector address, which normally has separate components whichrespectively identify the Flash chip within the memory subsystem, theFlash block within the Flash chip, and the physical sector within theFlash block of the memory 20 to which the physical sector is written.

Within the system 10 shown, data may only be written to a physicalsector if the sector has previously been erased. The Flash memory 20 iserased in response to a command at the physical interface in units of aFlash block, which typically includes 32 physical sectors. The relativetimes for performing operations within the Flash system 10 to read aphysical sector, program a physical sector, and erase a Flash block aretypically in the ratio 1:20:200.

In the arrangement of FIG. 2 the controller 16 is a Cyclic Storagecontroller which is a Flash media management controller in which amethod of ensuring uniformity of distribution of use is implementedwherein the media management algorithms which implement this method areimplemented as firmware by a processor within the controller.

With reference to FIG. 3 there is shown optimized hardware architecturewhich is defined for the cyclic Storage controller 16. In this case thecontroller hardware is a dedicated architecture in a separate integratedcircuit.

The controller 16 comprises host interface control block 22,microprocessor 24, flash interface control block 26, ROM 28, SRAM 30 andexpansion port 32, each of these being inter-connected by memory accesscontrol bus 34.

Cyclic Storage Flash media management algorithms are implemented byfirmware running on microprocessor 24 and the controller 16 isresponsible for all Flash media management functions and for thecharacteristics of the logical interface 14 presented to host 12.

The host interface control block 22 provides the path for data flow toand from host system 12 via logical interface 14.

As, in this case, the controller 16 is in the form of a dedicatedintegrated circuit the host interface control block 22 provides logicalinterface 14 which conforms to an industry standard protocol as well asa command register and set of taskfile registers which provide the routefor the microprocessor 24 to control the logical characteristics of theinterface 14.

The host interface control block 22 also allows for a sector of data tobe transferred in either direction across the logical interface 14between to the host system 12 and the controller's SRAM 30 by a directmemory access (DMA) operation without intervention from themicroprocessor 24.

The Flash interface control block 26 provides the path for data flow toand from Flash memory 20, and controls all operations which take placein the Flash memory 20. The operations taking place in Flash memory 20are defined and initiated by the microprocessor 24, which loadsparameter and address information to the flash interface control block26.

The set of operations which typically take place are the transfer of aphysical sector to Flash memory 20, the transfer of a physical sectorfrom Flash memory 20, the programming of a physical sector into flashmemory 20, the erasing of a Flash block, and the reading of the statusof flash memory 20.

Similarly a physical sector of data may be transferred in eitherdirector across the physical interface 16 between the Flash memory 20and the controller's SRAM 30 by DMA operations without intervention fromthe microprocessor 24. The organization of the 512 bytes of host dataand 16 bytes of overhead data within a physical sector which istransferred to Flash memory 20 is determined within the Flash interfacecontrol block 26, under the control of parameters loaded by themicroprocessor 24.

The Flash interface control block 26 also generates a 12-byte errorcorrecting code (ECC) which is transferred to Flash memory 20 andprogrammed as overhead data within each physical sector, and which isalso verified when a physical sector is transferred from Flash memory20.

The microprocessor 24 controls the flow of data sectors through thememory access control bus, or datapath, 34 or of the controller 16,implements the Flash media management algorithms which define thesector, controls data storage organization in the Flash memory 20, anddefines the characteristics of the logical interface 14 to host system12. In this case the microprocessor 24 is a 32-bit RISC processor.

The memory access control bus 34 allows transfer of information betweenthe microprocessor 24, host interface control block 22, and the Flashinterface control blocks 16, as well as between the host interfacecontrol block 22, the flash interface control block 26 and a memoryblock 30.

The microprocessor 24, host interface control block 22, and Flashinterface control block 26 may each be the master for a transaction onthe memory access control bus 34. Bus access is granted to requestingmasters on a cycle-by-cycle basis.

The SRAM block 30 stores all temporary information within the controller16, this storing function includes the buffering of sector data andstorage of control data structures and variables, as well as firmwarecode.

The ROM 28 is included in the controller 16 for storage of code forexecution by the microprocessor 24, or of information required by otherhardware blocks within the controller.

The inclusion in the controller architecture of an expansion port 32gives access to external hardware functions, RAM or ROM from the memorysystem 10.

During the operation of the controller all sector data being transferredbetween the logical interface 14 to host system 12, and the physicalinterface 18 to Flash memory 20 is buffered in the SRAM 30. Sufficientcapacity in the SRAM 30 is allocated for buffering of two sectors ofdata to allow concurrent transfers of successive sectors at the host andFlash interfaces. Data transfer between the logical host interface 14and SRAM 30 is performed by DMA with the host interface control block 22acting as bus master.

Data transfer between the physical Flash interface 18 and SRAM 30 isperformed by DMA with the Flash interface control block 26 acting as busmaster. Data to be written to sectors in Flash memory 20 is stored inthe SRAM memory 30 and is transferred by direct memory access under thecontrol of the Flash interface control block 26 via the physicalinterface to Flash memory 18. 512 bytes of user data to be written in asector had previously been supplied by host system 12 via the logicalinterface 14 and had been transferred by direct memory access under thecontrol of the host interface control block 22 to the SRAM memory 30.Programming of data in a sector in Flash memory 20 is accomplished bythe controller 16 by sending an address and command sequence at thephysical interface 18, followed by 528 bytes of-data plus ECC, followedby a program command code.

The transfer of data for a sector between a host system and thecontroller's SRAM 30, and between the SRAM 30 and Flash memory, iscontrolled by firmware running on the microprocessor 24 with thecontroller 16 being responsible for all Flash media management functionsand for the characteristics of the logical interface 14 present to host12.

As the controller 16 is in the form of a dedicated integrated circuit,the host interface control block 22 provides a logical interface whichconforms to an industry standard protocol, and a command register andset of taskfile registers provide the route for the microprocessor 24 tocontrol the logical characteristics of the interface 14. Command,address and parameter information is written to these task fileregisters by the host 12, and read by the microprocessor 24 forexecution of the command. Information is also been written to theregisters by the microprocessor 24 for return to the host 12.

In FIG. 4 there is illustrated the layered structure of the firmwarewhich performs the Cyclic Storage Flash media management operations. Thefirmware has three layers, the first being the host interface layer 40,the second layer 42 comprising the sector transfer sequencer 42 a andthe media management layer 42 b and the third being the flash controllayer 44.

These three firmware layers 40, 42 and 44 control the transfer of datasectors between the logical interface 14 to host 12 and the physicalinterface 18 to Flash memory 20. However, the firmware layers do notdirectly pass data, instead data sectors are transferred by the hardwareblocks of the controller 16 and therefore do not pass through themicroprocessor 24.

The host interface layer 40 supports the full command set for the hostprotocol. It interprets commands at the host interface 14, controls thelogical behavior of the interface 14 according to host protocols,executes host commands not associated with the transfer of data, andpasses host commands which relate to data in Flash memory to be invokedin the layers below. Examples of such commands are.

-   -   Read logical sector (single or multiple),    -   Write logical sector (single or multiple),    -   Erase logical sector (single or multiple), as well as other disk        formatting and identification commands.

The sector transfer sequencer 42 a receives interpreted commandsrelating to logical data sectors from the host interface layer 40 andthus invokes the Flash media management layer 42 b for logical tophysical transformation operations, and invokes the Flash control layer44 for physical sector transfers to or from Flash memory. The sectortransfer sequencer 42 a also performs sector buffer memory management.Another function of the sequencer 42 a is to create a sequence of sectortransfers, at the host interface 14 and Flash memory interface 18, and asequence of operations in the media management layer 42 b, in accordancewith the command received from the host 12 and the level of concurrentoperations which is configured for the Flash memory 20.

The media management layer 42 b performs the logical to physicaltransformation operations which are required to support the write, reador erasure of a single logical sector. This layer is responsible for theimplementation of Cyclic Storage media management algorithms.

The Flash control layer 44 configures the Flash interface control block26 hardware to execute operations according to calls from the sectortransfer sequencer 42 a or media management layer 42 b.

The media management functions which are implemented within the mediamanagement layer 42 b of the controller firmware create the logicalcharacteristics of a disk storage device in the memory system 10 whichuses Flash semiconductor memory 20 as the physical data storage medium.

The effectiveness of the media management performed by the mediamanagement functions of the media management layer 42 b is measured byits speed for performing sustained writing of data to the memory system10, its efficiency in maintaining its level of performance whenoperating with different file systems, and in this case, in host 12, andthe long-term reliability of the Flash memory 20.

Data write speed is defined as the speed which can be sustained whenwriting a large volume of contiguous data to the memory system 10. Insome cases, when the sustained data write rate of a memory system isbeing tested, the volume of data to be written may exceed the capacityof the memory system 10 and therefore logical addresses may be repeated.

Sustained write speed is determined by the sector data transfer speed atthe logical interface 14 to the host 12, and the physical interface 18to Flash memory 20, as well as the overhead percentage of accesses toFlash memory 20 at the physical interface 18 for Flash page read andwrite operations and Flash block erase operations which are not directlyassociated with storage of data sectors written by the host 12 at thelogical interface 14. In this case the control data structures andalgorithms which are employed should ensure that access to Flash memory20 for control functions is required at a much lower frequency than forhost sector write. The sustained write speed is also determined by theprocessing time within the controller 16 for media managementoperations, and the page read and program times, and block erase timeswithin the Flash memory 20.

In order for the memory system to operate efficiently when having filesystems with different characteristics, the Media management algorithmsfor the organization of host data and control data structures on Flashmemory 30 are appropriately defined and data write performance ismaintained in each environment.

In a first embodiment, the file systems implementing the MS-DOS standardare provided with at least one of the following characteristics: thehost 12 writing data sectors in clusters using multiple sector writecommands; the host 12 writing data sectors using single sector writecommands; the host 12 writing some sectors with single sector writecommands in an address space which is shared with clustered file data;the host 12 writing non-contiguous sectors for MS-DOS director and FATentries with single sector write commands; the host 12 writingnon-contiguous sectors for MS-DOS directory and FAT entries interspersedwith contiguous sectors for file data; and/or the host may rewritesectors for MS-DOS directory and FAT entries on a frequent basis.

It is a feature of flash memory, and in this case the Flash memory 20 ofthe memory system 10, that it has a wear-out mechanism within thephysical structure of its cells whereby a block of flash memory mayexperience failure after a cumulative number of operations. Typically,this is in the range of 100,000 to 1,000,000 program/erase cycles. Inlight of this the cyclic storage controller 16 of the presentarrangement implements a process of wear-leveling to ensure that“hot-spots” do not occur in the physical address space of the Flashmemory 20 and that utilization of Flash blocks is uniformly distributedover a prolonged period of operation.

Cyclic Storage media management algorithms are implemented within memorysystem 10 and perform the Media management operation of the physicalFlash memory 20 within the system 10. The cyclic storage mediamanagement algorithms comprise four separate algorithms, namely the DataWrite algorithm which controls the location for writing host informationto, the Block Erase algorithm which controls erasure of areas of Flashmemory 20 containing obsolete information, the Block Sequencingalgorithm which controls the sequence of use of Flash blocks for storinginformation, and the Address Translation algorithm which controls themapping of host logical addresses to physical memory addresses.

The method of Cyclic Storage media management implemented by thesealgorithms embodies the principle that data is written at physicalsector locations in Flash memory 20 which follow the same order as thesequence in which the data is written. This is achieved by writing eachlogical data sector at a physical sector position defined by a cyclicwrite pointer.

A schematic representation of the write operation of the cyclic storagemedia management method is shown in FIG. 5A. The write pointer, in thiscase data write pointer (DWP) 46 moves sequentially through the sectorpositions of Flash block X in Flash memory 20, and continues through thechain of blocks & and Z in a manner defined by the block sequencingalgorithm. Each block X, Y and Z is a physical structure in Flash memory20 which, in this case, comprises 32 sector locations which can beerased in a single operation.

As is illustrated in FIG. 5B logical data sectors are generally writtenin files by a file system in the host 12, and the Cyclic Storage DataWrite Algorithm locates the first sector of a file at the next availablephysical sector position following the last sector of the precedingfile. When a file is written by host 12 using logical sectors for whichvalid data already exists in the device, the previous versions of thesectors become obsolete and the blocks containing them are erasedaccording to the Block Erase Algorithm. In order to erase a blockcontaining obsolete file sectors it is, in some cases necessary torelocate some valid sectors of another file. This generally occurs whena block includes sectors of the head of a file, as well as sectors withunrelated logical addresses from the tail of a different file.

A second write pointer in this case data relocate pointer DRP 47 is usedfor writing relocated sectors in order to avoid sectors of one filefragmenting a block containing sectors of another file. The use of aseparate relocation pointer significantly reduces the fragmentation ofblocks containing a file, leading to minimum requirement for sectorrelocation and consequent maximum file write performance.

A host file system is used which also writes sectors containing systeminformation, such as directory or FAT sectors in the DOS file system,and these are generally written immediately before and after a group ofsectors forming a file. A separate system pointer, system write pointerSWP 48 is used for this host file system in order to define the physicalwrite location for system sectors, which are identified by their logicaladdress, in order to separate system sectors from file data sectors andavoid them being treated in the same way. This avoids a small group ofsystem sectors being “sandwiched” between the tail of one file and thehead of another. These system sectors contain information about manyfiles, and are generally re-written much more frequently than data for afile. “Sandwiched” system sectors would cause frequent relocation offile data sectors and thus the use of system pointer SWP 48 minimizesthe requirement for data sector relocation and maximizes file writeperformance.

A fourth pointer, system relocate pointer SRP 49 is used for relocationof system sectors, analogous to the relocation pointer DRP 47 for filedata sectors.

To summarize, the four write pointers are:

-   -   Data write pointer, DWP 46 which is used to define the physical        location for writing file data sectors transmitted by a host        system;    -   System write pointer, SWP 48 which is used to define the        physical location for writing system sectors transmitted by a        host system wherein system sectors are identified by their        logical address, in accordance with the characteristics of the        host file system in use;    -   Data relocation pointer, DRP 47 which is used to define the        physical location for writing file data sectors which must        occasionally be relocated prior to a block erasure for recovery        of capacity occupied by obsolete file data sectors; and    -   System relocation pointer, SRP 49 which is used to define the        physical location for writing system sectors which are being        relocated prior to a block erasure for recovery of capacity        occupied by obsolete system sectors.

A block must contain data associated with only a single write pointerand this results in four separate chains of blocks existing, one foreach write pointer. However, the same write and relocation algorithms ofthe cyclic storage algorithms apply to each write pointer 46, 47, 48 and49.

This scheme for locating a sector to be written at the first availablelocation following the preceding sector, combined with usage of multiplewrite pointers, is fully flexible, and provides high performance andtotal compatibility for all host write configurations, including singlesector data and data in clusters of any size.

However, the Cyclic Storage media management method is defined not toallow the existence of a large number of obsolete data sectors and norto implement background operations for functions such as garbagecollection. Typically only two blocks containing obsolete sectors areallowed to exist for each of the Data Write Pointer DWP 46 and SystemWrite Pointer SWP 48, and block erasure is performed as a foregroundoperation during sector write sequences.

This method of management means that the logical capacity of the flashmemory does not have to be reduced to allow for the existence of a largevolume of obsolete data, the data integrity is significantly improved bythe absence of background operations, which are susceptible tointerruption by power-down initiated by the host; and the pauses in datawrite sequences are short because erase operations are required for onlya single block at a time.

If an obsolete data sector is created in a new block associated witheither of the write pointers, then the existing “obsolete block” iseliminated by erasure, following sector relocation within the blocks ifrequired.

Erase sector commands sent from a host 12 are supported by marking thetarget sector as obsolete, and allowing its erasure to follow accordingto the Block Erasure algorithm.

The Cyclic Storage block sequencing algorithm determines the sequence inwhich blocks within the flash memory 20 are used for the writing of newor relocated data, and is therefore responsible for ensuring that noblock experiences a number of write/erase cycles which exceeds theendurance limit specified for the Flash memory system 10 which is beingused.

When a logical sector is written by the host, any previous version whichexists in the memories system is treated as obsolete data. The blockerase algorithm ensures that blocks which contain obsolete data sectorsare erased immediately, to allow recovery of the capacity occupied bythese sectors. The physical memory capacity of the system 10 istherefore occupied by valid data for logical sectors written by thehost, plus a small number of proprietary Cyclic Storage control datastructures and a number of erased blocks. Immediately after initialformatting, of the flash memory 20 the capacity of the memory 20consists almost entirely of erased blocks. When the host 12 has writtenat least once to all sectors in its logical address space, the die isconsidered to be logically full and its physical capacity is occupiedalmost entirely by valid data sectors, with a small number of erasedblocks maintained for correct device operation. An increased number oferased blocks will be created only if the host 12 executes commands toerase logical sectors.

Erased blocks which are allocated for use by one of the write pointers,or for storage of control data structures are taken from a pool ofavailable erased blocks. A block is never erased in response to a needto perform a write operation to that specific block, the blocksequencing algorithm determines the order of allocation for data writeoperations of blocks in the erased pool. The next available blockaccording to the algorithm is allocated, independent of whether therequirement is for use by one of the write pointers or for a controldata structure.

The implementation of these algorithms which perform the cyclic storagemedia management allows increased system flexibility by operating onindividual sectors of the flash memory 20 and separately tracking thelogical to physical address mapping of every sector in its logicaladdress space. A sector address table is maintained in the Flash memory20 which includes the physical address for every logical sector. Inaddition, every sector is written with a header containing its logicaladdress, providing a means of verifying sector identity and ensuringmaximum data integrity.

The data write algorithm, with its use of cyclic write pointers,provides the capability for tracking the sequence of sector writingusing the logical addresses in the headers of sectors in sequentialphysical positions. This feature provides total data security even whenthe logical to physical address mapping records for recently writtensectors are temporarily held in volatile controller memory SRAM 30 andnot in Flash memory 20. Such temporary records can be reconstructed fromthe data sectors in Flash memory 20 when a system 10 in which the CyclicStorage algorithms are implemented is initialized. It is thereforepossible for the sector address table in Flash memory 20 to be updatedon an infrequent basis, leading to a low percentage of overhead writeoperations for control data and a high sustained data write rate.

In FIG. 6 there is shown a schematic representation of the addresstranslation process which uses a three level hierarchy of mappingstructures 50 which is performed in the memory system 10.

The three levels of the hierarchy are the sector address table 52, thetemporary sector address table 54 and the sector address record 56.

The top level of the hierarchy of the mapping structures is the sectoraddress table 52, which is a master table containing a physical addressfor every logical sector stored in the system 10 and which is stored inFlash memory 20. Structures in the two lower levels of the hierarchy 54and 56 provide the means for reducing the frequency at which writeoperations must occur to the sector address table.

The sector address record 56 is a list stored in the controller'svolatile memory SRAM 30 of logically contiguous sectors which have beenwritten to system 10. This list allows the physical address of anylogical sector which it includes to be determined without need foraccess to Flash memory 20. It may also be reconstructed during deviceinitialization from the sequence of recently-written sectors which maybe traced in the Flash memory 20. The intermediate temporary sectoraddress table 54 is contained in Flash memory 20 and is updated with thecontents of the sector address record 56 when the list becomes full. Theintermediate temporary sector address table 54 is in the same format asthe sector address table 52, and allows physical address data updates tospecific blocks of the sector address table 52 to be accumulated toallow a more efficient table write process to be performed. Thetemporary table 54 allows the physical address of any logical sectorcontained in it to be determined without need for access to the sectoraddress table 52.

This hierarchy of mapping structures 50 is maintained with an infrequentrequirement for write operations to Flash memory and efficientlysupports logical to physical address translation in such a way thattotal security of sector address information is provided, even ifelectrical power is unpredictably removed from the system 10.

The data structures required to support the Cyclic Storage mediamanagement algorithms are stored principally in Flash memory 20 togetherwith the host data sectors, with only a very limited amount of controldata being held temporarily in the control processor's volatile RAM 30.Information held in the volatile memory 30 is non-critical, and can bereconstructed from Flash memory 20 if the power supply is interrupted.

The controller 16 in Flash memory system 10 as described above, mayoperate on only one array within the Flash memory 20 at a time. Eacharray is a group of Flash memory storage cells within which only asingle sector program operation or block erase operation may beperformed at any one time. In this case the array is a complete Flashchip. The controller is designed to be capable of performing programoperations concurrently on sectors within different arrays or eraseoperations concurrently on blocks within different arrays. Thecontroller 16 can address, program and check current status of any arraywithin the Flash memory 20 independently from others.

Each sector is a unit of physical storage in Flash memory 20 which isprogrammed in a single operation. In the present arrangement, whichcomprises NAND Flash memory chips, a sector equivalent to a page withinthe Flash array and has a capacity of 528 bytes. In this case, the eachFlash chip is considered to comprise four arrays, each of which can beprogrammed with one sector at any time.

The scheduling of transfer, i.e., the ordering of sector data iscontrolled by the sector transfer sequencer block 42 a shown in FIG. 4and is explained in greater detail with reference to FIGS. 7 to 11. Thetransfer of data at the host interface 14 is independent of transfer ofdata at the physical interface to Flash memory 18 of memory system 10,and the burst transfer rate at the host interface is determined by thehost 12. Several different methods of scheduling the transfer of sectordata maybe implemented by sector transfer sequencer firmware, dependingon the way in which blocks and pages in the Flash memory 20 areaddressed by the controller 16. The methods described assume that sectordata is supplied by the host and stored in SRAM 30 at a rate which issufficient to supply sector data for transfer to Flash memory 20 asdescribed.

With reference to FIG. 7, there is shown a first embodiment of a methodof scheduling the transfer of sector data which the controller may useto address blocks and pages within memory system 10 wherein Flash memory20 comprises four Flash arrays 0, 1, 2 and 3, where the controller 16 isrequired to initiate concurrent page program or block erase operationsin two arrays simultaneously. The arrays are linked in pairs, and thecorresponding blocks 0 with the same addresses within the linked arraysare treated as a single virtual block 0. As shown, block 0 in Flasharray 0 is linked with block 0 in Flash array 1 to form virtual block 0.The N blocks in each of Flash arrays 0 and 1 are linked to form Nvirtual blocks, labeled 0 to N−1, and the N blocks in each of Flasharrays 3 and 2 are linked to form a further N virtual blocks, labeled Nto 2N−1. The order of writing sectors within each virtual block isdetermined by the movement of the write pointer, which alternatesbetween the constituent blocks as it moves sequentially through thesectors in the virtual block.

In FIG. 8 there is shown a second embodiment of a method which thecontroller may use to address blocks and pages within memory system 10wherein Flash memory 20 comprises four Flash arrays, where it isnecessary for the controller 16 to initiate concurrent page program orblock erase operations in four arrays. All four arrays are linked, andthe corresponding blocks with the same addresses within each of thelinked arrays are treated as a single virtual block. As can be seen,blocks 0 in Flash arrays 0 to 3 are linked to form virtual block 0. TheN blocks in each of Flash arrays 0 to 3 are linked to form N virtualblocks, labeled 0 to N−1. The order of writing sectors within a virtualblock is determined by the movement of the write pointer, which movesthrough the corresponding sectors in blocks 0 to 3 and then incrementsto the next sector in block 0, as it moves sequentially through thesectors in the virtual block.

The blocks within the Individual Flash arrays which are linked to form avirtual block may themselves comprise multiple smaller adjacent physicalblocks which are stacked together.

Program operations may be performed substantially concurrently on onesector from each of the constituent blocks forming a virtual block.

With reference to FIG. 9, there is shown a third embodiment of a methodof concurrently programming sectors 0, 1, 2, and 3 which are shown inFlash arrays 0, 1, 2 and 3 of FIG. 8. Data for sector 0 is transferredbyte serially to Flash array 0 across the physical interface to Flashmemory 20, and then a program command is sent by the controller 12 toFlash array 0 to initiate the program operation. Whilst sector 0 isbeing programmed, the controller 12 transfers data for sector 1 to Flasharray 1 and initiates a program operation for it. The same is done forsectors 2 and 3. Sectors 0 to 3 are programmed in Flash arrays 0 to 3substantially concurrently with each other, and the speed oftransferring and programming data to sectors in the Flash memory is muchhigher than can be achieved by programming only one Flash array at atime. When the program operations in Flash arrays 0 to 3 have allcompleted, the process is repeated for sectors 4 to 7. A sharedbusy/ready line from the Flash arrays can be used to signal when allarrays have completed programming sectors 0 to 3 and when there is noFlash array active. However, the status of all the arrays canalternatively be polled independently.

In FIG. 10 there is shown a fourth embodiment of a sequence fortransferring sector data to and initiating programming operations inFlash arrays 0 to 3. The sequence described for sectors 0 to 3 withreference to FIG. 9 is performed, but upon the completion of theprogramming operation in a Flash array, sector data is immediatelytransferred for the following programming operation in that array. Thestatus of each array is polled independently to find when an operationin the array has completed. Alternatively, independent ready/busysignals from every array can be used. This increased pipelining of thesector data transfer and sector programming provides further increasedspeed for writing sector data in the Flash memory.

Each of these methods detailed in the above described embodiment may beused for writing sector data which is being relocated from anothersector in Flash memory, as well as sector data which has been suppliedby a host system.

The order of sectors being concurrently programmed in different Flasharrays need not follow the order shown in FIG. 8, that is, sequentialorder need not be used. It is possible to program any sector from aFlash array concurrently with any other sector from another array,provided that no two sectors from the same array are used. For example,it would be possible to transfer and then program a group of foursectors FIG. 8 in the order sector 10, sector 3, sector 1, then sector4. However, the use of a cyclic write pointer which moves sequentiallythrough the addresses of a virtual block means that it is most commonfor sector addresses to be in sequential order. The first sector of agroup of four for which data is being concurrently transferred andprogrammed need not be located in Flash array 0. The sectors may, forexample, be transferred in the order sector 2, sector 3, sector 4, andsector 5.

The write time for a cluster of sectors can be expressed as a functionof the transfer time to Flash memory 20 for sector data and programmingtime for a sector in Flash memory 20. The programming time is typically200 microseconds and is much longer than transfer time, which istypically about 30 microseconds. The time associated with flash chipaddressing and initiation of data transfer and programming by thecontroller is usually not significant. For the example shown in FIG. 9,cluster write time is given byCluster Write Time=8*Sector data transfer time+2*Programming time.

For the example shown in FIG. 10, cluster write time is given byCluster Write Time=5*Sector data transfer time+2*Programming time.

As detailed above, all 4 flash memory arrays are being accessed, howeverthis results in the electrical current level being high (=4*arraycurrent) as well as performance is on the maximum.

With reference to FIG. 11, there is illustrated a first embodiment of amethod of allowing the limiting of the number of flash memory arraysaccessed at a time in order to control the current. As can be seen, FIG.11 illustrates a pipelined sequence for transferring sector data to andinitiating programming operations in flash arrays 0 to 3 but the maximumnumber of active flash memory arrays is limited to three. The sequencedescribed for sectors 0 to 2 with reference to FIGS. 9 and 10 isperformed, but then the number of active arrays is three and thereforethe controller 16 waits for at least one of the arrays to be completed,in this case chip 0. Whenever the number of active arrays is lower thanthree, sector data is immediately transferred for the followingprogramming operation in the next chip. In other words, before accessingany flash array the number of currently active arrays is always checkedagainst the allowed limit which in this case is three. Thus, theelectrical current level is regulated.

For the example illustrated by FIG. 11 the cluster time will beCluster Write Time=4*Sector data transfer time+3*Programming Time

Similarly, the number of active arrays can be limited to two or one. Forthe same case of a 4-way interleaved memory system where the activearray limit is two (not shown) the cluster time will beCluster Write Time=5*Sector data transfer time+4*Programming Time.

A more complex method of performing the control of current can be usedwhen the flash memory 20 of the system 10 has different electricalparameters for different flash operations, i.e., the electricalparameters for read, transfer, programming and erase operations are alldifferent. For simplicity the arrays are as before, programmed innumerical order 0 to 3. The status of every array is polledindependently to find a time when the chip completed. Otherwise,independent ready/busy signals from every array can be used. This methoduses the same method of pipelining but creates extra on-purpose delay inorder to limit the electrical level.

The flash access control combined with the pipelining proves a veryefficient usage of flash memory performance and still gives a high speedfor writing sector data in the flash memory while limiting theelectrical power. The method allows a defined number of active arrays,in this case three, most of the time. The same method can be applied toany other flash operation like read and erase.

The maximum number of active memory arrays can be flexiblychanged/programmed by the host to define the ratio between writeperformance and electrical current level. Some hosts could implementthis by enabling standard-defined power management features and defininga level of compromise between power consumption and performance.However, some host systems may prefer slow memory devices with lowelectrical current levels, and in some cases even the same host systemmay prefer different combination of performance and power consumption indifferent operating modes. Each of these arrangements can be catered forusing the method described above.

Various modifications may be made to the arrangements as hereinbeforedescribed without departing from the scope of the invention. Forexample, a system which incorporates a flash disk device may bephysically partitioned in several ways, according to the systemarchitecture, however, all systems generally conform to the structuredescribed herein before. For example the flash memory 20 is shown inFIG. 2 as being part of a memory system 10, however, it mayalternatively be on a removable card and may connect to a host systemvia a logical interface 14 which as before conforms to industry standardprotocols. Examples of such industry standards being PCMCIA ATA, CompactFlash and MultiMediaCard. In such an arrangement the controller may beon a removable card in which case the controller is typically a singleintegrated circuit. The Flash memory 10 may consist of one or moreintegrated circuits and the controller may be integrated on the sameintegrated circuit as the Flash memory.

It could also be the case that the host and the flash system may bephysically partitioned such that only the Flash memory is on a removablecard, which has a physical interface to the host system. A hierarchy ofthis arrangement is shown in FIG. 12. An example of such a removableFlash memory card is SmartMedia. The controller is located within thehost system 11 and may take to form of an integrated circuit, or offirmware which is executed by a processor within the host system.

Alternatively the method of the present invention may be implemented inan embedded memory system which is not physically removable from a hostsystem. Such a system may have the same partitioning as is used for amemory system on a removable card, with the controller being in the formof an integrated circuit and with a logical interface conforming toindustry standard protocols. However, the controller may also beintegrated with other functions within the host system.

In the arrangement described, each sector is identified by a LBA,however, it may also be identified by an address in theCylinder/Head/Sector (CHS) format originally used with magnetic diskdevices. Also in the described arrangement the controller hardware isdedicated architecture in a separate integrated circuit, however,elements of the controller hardware, such as the microprocessor, may beshared with other functions within the host system. Additionally thecyclic storage management algorithm may be implemented in amicroprocessor within the host system or the process may be performedvia standard microprocessor input/output ports without any dedicatedcontroller hardware. If the controller is part of an embedded memorysystem and shares its microprocessor with other functions of a hostsystem, the logical interface for the control of the memory system maybe implemented directly within firmware executed by the processor, thismeans that hardware registers may be eliminated and variables may bepassed directly to a controller function which may be called a hostfunction within the firmware code.

In the flash memory system described previously, data transfer betweenthe host or flash interfaces and the SRAM are performed by DMA howeverin an alternative embodiment a separate memory block could be usedexclusively for buffering sector data. Typically this memory block couldbe a dual port RAM, with ports allocated independent access by the hostinterface control block and the flash interface control block.

In the described arrangement the memory blocks into which the memorysectors were arranged were described as being a physical structurewithin the flash memory comprising 16 sector locations, however it isalso possible that these memory blocks comprise 32 flash locations. Alsothe memory blocks can alternatively be virtual blocks comprisingphysical blocks distributed across multiple flash chips or multipleindependent arrays within the same chip which are erased in a singleoperation by the controller. Where a virtual block comprises M physicalblocks, each with capacity for N sector, the virtual block has capacityfor M*N sectors. A virtual block is treated in exactly the same way as aphysical block by the cyclic storage media management algorithms.

It should also be noted that the ROM and expansion port of thecontroller of the memory system are optional features and need not beincluded.

Furthermore, each array in the flash memory is described previously asbeing a complete flash chip, however, it is also the case that eacharray may be a constituent part of a chip, as some Flash chips such assome 512 Mbit NAND flash designs incorporate multiple arrays within achip and separate sector program operations may be independently startedin different arrays within the chip. Also in the description, pageswithin the flash array have been described as being equivalent to asector, however in some AND flash memory chips a page may comprise foursectors and have a capacity of 2112 bytes, in each case the page isprogrammed in a single operation. Additionally each group of sector datahas been described as being the first four sector data of a file,however it may alternatively be a file fragment. Also the host systemcan write data to the memory system in units of a cluster wherein eachcluster will be treated as the controller as an integral number ofgroups, as opposed to the data being written to the memory system assingle sectors.

Although the present invention has been described in terms of specificembodiments it is anticipated that alterations and modifications thereofwill no doubt become apparent to those skilled in the art. It istherefore intended that the following claims be interpreted as coveringall such alterations and modification as fall within the true spirit andscope of the invention.

1. A method of operating a memory system, comprising: initiating anoperation for access of two or more groups of memory cells; checking acurrent status of each of the two or more groups of memory cells duringthe operation; determining a number of the two or more groups of memorycells that are simultaneously active during the operation; delaying theoperation if the number of the two or more groups of memory cells thatare simultaneously active during the operation is at a particular value;and continuing with the operation if the number of the two or moregroups of memory cells that are simultaneously active during theoperation is below the particular value.
 2. The method of claim 1,further comprising: initiating a second operation for access of the twoor more groups of memory cells; checking a current status of each of thetwo or more groups of memory cells during the second operation;determining a number of the two or more groups of memory cells that aresimultaneously active during the second operation; delaying theoperation if the number of the two or more groups of memory cells thatare simultaneously active during the second operation is at a secondparticular value; and continuing with the second operation if the numberof the two or more groups of memory cells that are simultaneously activeduring the second operation is below the second particular value;wherein the second operation is different than the operation; whereinthe second particular value is different than the particular value; andwherein the operation and the second operation are selected from thegroup consisting of a read operation, a transfer operation, aprogramming operation, and an erase operation.
 3. The method of claim 1,further comprising delaying the operation even though the memory systemis capable of concurrent access of a number of groups of memory cells inexcess of the particular value.
 4. The method of claim 1, whereininitiating an operation for access of two or more groups of memory cellscomprises initiating an operation for access of two or more memoryarrays.
 5. The method of claim 1, wherein initiating an operation foraccess of two or more groups of memory cells comprises initiating anoperation for access of two or more memory chips.
 6. The method of claim1, wherein continuing with the operation if the number of the two ormore groups of memory cells that are simultaneously active during theoperation is below the particular value comprises accessing a next groupof memory cells while accessing a previous group of memory cells.
 7. Themethod of claim 1, further comprising: adjusting the particular value inresponse to electrical parameters for the operation.
 8. The method ofclaim 7, wherein adjusting the particular value in response toelectrical parameters for the operation comprises adjusting theparticular value to maintain an electrical current level of the memorysystem below a particular value during the operation.
 9. The method ofclaim 7, wherein adjusting the particular value in response toelectrical parameters for the operation comprises adjusting theparticular value to maintain a particular ratio between performance andpower consumption.
 10. The method of claim 1, wherein initiating anoperation for access of two or more groups of memory cells comprisesinitiating an operation for access of two or more groups of memory cellswherein only one access can be performed at any one time in each of thetwo or more groups of memory cells.
 11. A method of operating a memorysystem, comprising: initiating a sequential access of two or more groupsof memory cells; determining an electrical current level of the accessedgroups of memory cells; delaying access of one of the groups of memorycells if a next access in the sequence would exceed a particular valueof the electrical current level; and continuing with the sequentialaccess when the next access in the sequence would produce an electricalcurrent level below the particular value.
 12. The method of claim 11,wherein initiating a sequential access of two or more groups of memorycells comprises: initiating transfer of first data for a first group ofmemory cells; initiating programming of the first data to the firstgroup of memory cells; initiating transfer of second data for a secondgroup of memory cells while programming the first data to the firstgroup of memory cells; and initiating programming of the second data tothe second group of memory cells while programming the first data to thefirst group of memory cells.
 13. The method of claim 12, whereininitiating a sequential access of two or more groups of memory cellsfurther comprises: initiating transfer of third data for a third groupof memory cells while programming the first data to the first group ofmemory cells and while programming the second data to the second groupof memory cells; and initiating programming of the third data to thethird group of memory cells while programming the first data to thefirst group of memory cells and while programming the second data to thesecond group of memory cells.
 14. The method of claim 12, whereininitiating a sequential access of two or more groups of memory cellsfurther comprises: initiating transfer of third data for a third groupof memory cells while programming the second data to the second group ofmemory cells and after completion of programming the first data to thefirst group of memory cells; and initiating programming of the thirddata to the third group of memory cells while programming the seconddata to the second group of memory cells.
 15. A method of operating amemory system, comprising: initiating a sequential access of two or moregroups of memory cells; determining a number of the two or more groupsof memory cells that are simultaneously active during the sequentialaccess; delaying access of a next group of memory cells in the sequenceif the number of the two or more groups of memory cells that aresimultaneously active during the sequential access is at a particularvalue; and accessing the next group of memory cells in the sequence whenthe number of the two or more groups of memory cells that aresimultaneously active during the sequential access is below theparticular value.
 16. The method of claim 15, wherein initiating asequential access of two or more groups of memory cells comprises:initiating transfer of first data for a first group of memory cells;initiating programming of the first data to the first group of memorycells; initiating transfer of second data for a second group of memorycells while programming the first data to the first group of memorycells; and initiating programming of the second data to the second groupof memory cells while programming the first data to the first group ofmemory cells.
 17. The method of claim 16, wherein delaying access of anext group of memory cells in the sequence comprises: delaying transferof third data for a third group of memory cells until programming of thefirst data to the first group of memory cells is completed, if theparticular value is two.
 18. The method of claim 15, wherein accessingthe next group of memory cells in the sequence when the number of thetwo or more groups of memory cells that are simultaneously active duringthe sequential access is below the particular value comprises accessingthe next group of memory cells while continuing to access a previousgroup of memory cells.
 19. The method of claim 15, further comprisingdelaying access of the next group of memory cells in the sequence eventhough the memory system is capable of accessing the next group ofmemory cells.
 20. The method of claim 15, further comprising adjustingthe particular value in response to a type of access being performed.